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Si5040
>0 transition in a
No
1024-bit field
Yes
Increment
Reset
Counter
Count
Is Count > dLosClearThresh *16 +1
No
Yes
Clear dLos
Figure 11. Algorithm to Clear dLOS
The receiver may be programmed to perform any of the following consequent actions upon declaring RX_LOS:
1. Lock the receiver to the applied reference clock (lock to reference): ltrOnLOS bit in Register 7.
2. Assert receiver loss of lock (LOL): lolOnLOS bit in Register 7.
3. Disable (squelch) the receive data output (RD): SquelchOnRxLOS bit in Register 28.
4. Generate a clock pattern at the receive data output (RD): clkOnLOS bit in Register 28.
For different combinations of ltrOnLOS and lolOnLOS settings in Register 7, the device may behave differently in
the CDR lock acquisition process. Refer to Figure 12 and Figure 13 for more details on CDR and VCO behaviors
upon declaring LOS. ltrOnLOS = 0, lolOnLOS = 0, and VCOCAL[1:0] = 10 binary by default.
Rev. 1.3
21
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